University of Toronto

Research exchange

AD/DAC design

Qualcomm

Senior Hardware Engineer

mixed signal IC designs for wireless commnucations

Cadence Design Systems

Senior Engineer

Responsible for Physical Verification.

QUALCOMM Inc

Staff Engineer

analog mixed signal IC designs.

CUHK

Ph.D.

Research on low power mixed signal IC design.

A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches

Circuits and Systems I: Regular Papers, IEEE Transactions on

A high-precision capacitance-to-digital converter (CDC) that is configurable to interface with unipolar or push-pull-type capacitive sensors is presented in this paper. In the conventional switched-capacitor CDC, it is well known that clock feedthroughs and charge injections from top-plate switches can be eliminated by a bottom-plate sampling scheme. However, those charge errors from the bottom-plate switches depend on the digital output and the varying value of the sensing capacitor itself. They will thus affect the overall CDC linearity. When the varying range of the sensing capacitor is wide, the nonlinearity becomes more pronounced. This paper proposes new switching and calibration schemes to reduce these non-idealities. A prototype of a second order CDC employing the proposed techniques in a 0.18 $mu$m CMOS process achieves a 53.2 aF RMS resolution with a 1 ms conversion time. The proposed calibration technique improves the linearity of the CDC from 9.3 bits to 12.3 bits and from 10.1 bits to 13.3 bits in the unipolar and push-pull-type sensing modes, respectively, with a sensing capacitance varying from 0.5 to 3.5 pF. The CDC is also demonstrated with a real-life pressure sensor.

A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches

Circuits and Systems I: Regular Papers, IEEE Transactions on

A high-precision capacitance-to-digital converter (CDC) that is configurable to interface with unipolar or push-pull-type capacitive sensors is presented in this paper. In the conventional switched-capacitor CDC, it is well known that clock feedthroughs and charge injections from top-plate switches can be eliminated by a bottom-plate sampling scheme. However, those charge errors from the bottom-plate switches depend on the digital output and the varying value of the sensing capacitor itself. They will thus affect the overall CDC linearity. When the varying range of the sensing capacitor is wide, the nonlinearity becomes more pronounced. This paper proposes new switching and calibration schemes to reduce these non-idealities. A prototype of a second order CDC employing the proposed techniques in a 0.18 $mu$m CMOS process achieves a 53.2 aF RMS resolution with a 1 ms conversion time. The proposed calibration technique improves the linearity of the CDC from 9.3 bits to 12.3 bits and from 10.1 bits to 13.3 bits in the unipolar and push-pull-type sensing modes, respectively, with a sensing capacitance varying from 0.5 to 3.5 pF. The CDC is also demonstrated with a real-life pressure sensor.

A charge recycling SAR ADC with a LSB-down switching scheme

Circuits and Systems I: Regular Papers, IEEE Transactions on

A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches

Circuits and Systems I: Regular Papers, IEEE Transactions on

A high-precision capacitance-to-digital converter (CDC) that is configurable to interface with unipolar or push-pull-type capacitive sensors is presented in this paper. In the conventional switched-capacitor CDC, it is well known that clock feedthroughs and charge injections from top-plate switches can be eliminated by a bottom-plate sampling scheme. However, those charge errors from the bottom-plate switches depend on the digital output and the varying value of the sensing capacitor itself. They will thus affect the overall CDC linearity. When the varying range of the sensing capacitor is wide, the nonlinearity becomes more pronounced. This paper proposes new switching and calibration schemes to reduce these non-idealities. A prototype of a second order CDC employing the proposed techniques in a 0.18 $mu$m CMOS process achieves a 53.2 aF RMS resolution with a 1 ms conversion time. The proposed calibration technique improves the linearity of the CDC from 9.3 bits to 12.3 bits and from 10.1 bits to 13.3 bits in the unipolar and push-pull-type sensing modes, respectively, with a sensing capacitance varying from 0.5 to 3.5 pF. The CDC is also demonstrated with a real-life pressure sensor.

A charge recycling SAR ADC with a LSB-down switching scheme

Circuits and Systems I: Regular Papers, IEEE Transactions on

Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications

Circuits and Systems II: Express Briefs, IEEE Transactions on

The successive approximation register (SAR) analog-to-digital converters (ADCs) outperform other types of ADCs on the area and energy efficiency due to its binary searching algorithm, which however has a conversion speed limitation. When pipelining multiple SAR ADCs, the speed is improved, the resolutions in individual stages are relaxed, and the nonidealities from non-first stages are desensitized by the gains preceding them. This brief examines the effects of the stage resolution on linearity, noise, speed, area, and power consumption in pipelined SAR ADCs. Two conclusions are reached. First, under certain cases, a larger resolution per stage improves the ADC linearity without costing the speed of the operational amplifiers (op-amps) used for residue amplifications. However, the stage resolution does not affect the op-amp open-loop gain requirement. Second, for area and power consideration, allocating about one quarter of the overall number of bits to the first stage is optimum in the practical situation that the area and power of the active circuitries are tens or hundreds of times of those of the unit capacitors in the SAR sub-ADCs.